At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Nous recherchons un(e) stagiaire en modélisation pour développer des modèles TLM des composants du Secure Element et valider le mode d'exécution XIP. Le rôle aura un impact direct sur l'optimisation des performances et la fiabilité des systèmes, en combinant modélisation SystemC, co-simulation RTL et analyse PPA. Vous participerez à l'ensemble du cycle, de la modélisation à la présentation des résultats. Missions principales : Développer des modèles TLM (SystemC ou Python) des composants du Secure Element (CPU, RAM, Flash, bus, mailboxes) à partir des RTL existantes. Implémenter et valider le mode d'exécution XIP (execution directe depuis la flash) dans le modèle SystemC. Intégrer et exécuter la co-simulation entre SystemC et RTL sous Cadence Xcelium en utilisant des scénarios firmware existants. Collecter et comparer les métriques de performance, puissance et surface (PPA) entre les configurations XIP et non-XIP. Présenter une démonstration finale de co-simulation et rédiger un rapport technique détaillant la méthodologie, les résultats et les recommandations. Qualifications requises : Diplôme en électronique, microélectronique ou domaine équivalent. Connaissance des outils de simulation Cadence Xcelium et expérience en analyse PPA. Connaissances en modélisation SystemC et co-simulation RTL. Maîtrise de Python et/ou SystemC Connaissances des architectures hardware design. Connaissances en cryptographie. La maîtrise de l'anglais. Cadence s'engage en faveur de l'égalité des chances et de l'équité en matière d'emploi à tous les niveaux de l'organisation. Nous nous efforçons d'attirer un vivier de candidats qualifiés et diversifié et encourageons la diversité et l'inclusion sur le lieu de travail. English version below We are seeking an intern to develop TLM models of Secure Element components and validate the XIP execution mode. This role will directly impact system performance and reliability by combining SystemC modeling, RTL co-simulation, and PPA analysis. You will be involved throughout the full cycle, from modeling to results presentation. Key Responsibilities: Develop TLM (SystemC or Python) models of Secure Element components (CPU, RAM, Flash, bus, mailboxes) based on existing RTL. Implement and validate the XIP execution mode (direct execution from flash) within the SystemC model. Integrate and run co-simulation between SystemC and RTL in Cadence Xcelium using existing firmware scenarios. Collect and compare performance, power, and area (PPA) metrics between XIP and non-XIP configurations. Deliver a final co-simulation demo and produce a technical report summarizing methodology, results, and recommendations. Qualifications : Degree in Electronics, Computer Science, Microelectronics, or a related field. Knowledge of Cadence Xcelium simulation tools and experience in PPA analysis. Knowledge of SystemC modeling and RTL co-simulation. Proficiency in Python and/or SystemC. Knowledge of hardware design architectures. Knowledge of cryptography. Fluency in English. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. We're doing work that matters. Help us solve what others can't. Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs) Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/equal-employment-opportunity-policy.pdf) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. ? Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
En cliquant sur "JE DÉPOSE MON CV", vous acceptez nos CGU et déclarez avoir pris connaissance de la politique de protection des données du site jobijoba.com.