Research engineer in optimization and design space exploration for next-generation computing systems h/f

Le CEA est un acteur majeur de la recherche, au service des citoyens, de l'économie et de l'Etat.

Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s'engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l'Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.

Implanté au coeur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d'un large éventail de partenaires académiques et industriels en France, en Europe et à l'international.

Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :

- La conscience des responsabilités
- La coopération
- La curiosité IN SUMMARY, WHAT DO WE OFFER YOU?
We are looking for an Research Engineer in optimization and Design Space Exploration for Next-Generation Computing Systems. This position in fixed-term contact is based at Nano-Innov (CEA Paris-Saclay), Essonne (91). This position is available as soon as possible.
Context
Modern computing systems ranging from high-performance computing (HPC) to embedded AI and automotive platforms face increasingly complex and interdependent design challenges. These systems must meet strict constraints on performance, power, area, cost, and reliability, all while adapting to rapidly evolving workloads and technologies.
The design process involves both hardware architecture choices (e.g., cores, memory hierarchy, accelerators, interconnects) and software-level decisions (e.g., task mapping, scheduling, compiler optimizations), which together lead to a combinatorial explosion of possible configurations.
Exploring these vast and heterogeneous design spaces is computationally demanding, often requiring costly simulations and automated optimization loops to efficiently navigate trade-offs and identify optimal or near-optimal solutions.
To address these challenges, CEA has developed A-DECA (Architecture Design Exploration and Configuration Automation), an in-house Electronic Design Automation (EDA) framework. A-DECA provides a modular, flexible, and multi-objective design space exploration environment for architecture-level decision making. IT enables early, automated evaluation of hardware/software configurations for HPC, AI, and automotive systems.
Research Objectives
You will contribute to the development of next-generation optimization methodologies integrated into the A-DECA framework.
The focus is on exploration strategies that GO beyond traditional techniques such as linear programming or deterministic solvers.
You will work on cutting-edge methods including :
Bayesian optimization
Surrogate modeling to accelerate evaluation of costly simulations
Genetic algorithms and other evolutionary techniques to generate a diverse set of high-performing solutions.
You will design and implement new optimization techniques capable of handling :
Extremely large design spaces with many interacting variables
Multi-objective trade-offs (performance, power, area, sustainability, etc.)
Complex constraints and architectural decisions typical of real-world electronic systems
Your work will enable the automatic generation of optimized and diversified architecture configurations, and provide insightful trade-off analysis across the design space.
Validation & Applications
The methods developed will BE tested and validated on :
Various benchmarks to assess performance, scalability, and robustness
Real-world case studies from national and European R&D projects
Industrial use cases including architecture exploration for HPC and AI accelerators
Cross-domain applications such as automotive
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